ASIC Design Engineer - Cadence, VHDL, Verilog

We are searching for an ASIC digital design engineer for tasks relating to the design implementation and verification of the digital MAC layer of a wireless communication ASIC. You will need experience of VHDL, Cadence digital simulation tools and ideally some knowledge of Verilog. This is a 12 month project onsite with our client, a leading vendor within the semiconductor sector. Good rates offered, please Apply to discuss. Our client has indicated that this contract is very likely to be extended for good performers. ## Type : Contract ## Location : Flanders, Belgium